1. Field of the Invention
This invention relates generally to phase-locked loops and, more particularly, to a system and method for acquiring and tracking a data signal with a voltage controlled oscillator (VCO) having selectable frequency ranges and a selectable frequency sweep window.
2. Description of the Related Art
Phase-locked loops (PLLs) and clock recovery circuits (CRCs) find wide application in areas such as communications, wireless systems, digital circuits, and disk drive electronics (parts of the following background are excerpts from Behzad Ravavi, xe2x80x9cDesign of Monolithic Phase-Locked Loops and Clock Recovery Circuitsxe2x80x94A Tutorialxe2x80x9d). While the concept of phase locking has been in use for more than half a century, monolithic implementation of PLLs and CRCs has become possible only in the last twenty years, and popular in the last ten years. Two factors account for this trend: the demand for higher performance and lower cost in electronic systems, and the advance of integrated-circuit (IC) technologies in terms of speed and complexity.
In many systems, data is transmitted or retrieved without any additional timing reference. In optical communications, for example, a stream of data flows over a single fiber with no accompanying clock, but the receiver must eventually process the data synchronously. Thus, the timing information (e.g., the clock) must be recovered from the data at the receive end. Most clock recovery circuits employ phase locking.
An ideal voltage-controlled oscillator (VCO) generates a periodic output whose frequency is a linear function of a control voltage xcexdcont:
xcfx89out=wFR+KVCOVcont
where xcfx89FR is the xe2x80x9cfree-runningxe2x80x9d frequency and KVCO is the xe2x80x9cgainxe2x80x9d of the VCO (specified in rad/s/V). Since phase is the time integral of frequency, the output of a sinusoidal VCO can be expressed as:
y(t)=A cos(xcfx89FRt+KVCO∫xe2x88x9200tVcontdt).
In practical VCOs, KVCO exhibits some dependence on the control voltage and eventually drops to zero as |Vcont| increases.
A VCO is considered to be a linear time-invariant system, with the control voltage as the system""s input and the excess phase of the output signal as the system""s output. Since the excess phase is:
xcfx86out(t)=KVCO∫Vcontdt,
the input/output transfer function is:                     Φ        out            ⁡              (        s        )                            V        cont            ⁡              (        s        )              =                    K        VCO            s        .  
The above equation reveals an interesting property of VCOs: to change the output phase, we must first change the frequency and let the integration take place. For example, suppose for t less than t0, a VCO oscillates at the same frequency as a reference, but with a finite phase error. To reduce the error, the control voltage, Vcont, is stepped by +xcex94V at t=t0, thereby increasing the VCO frequency and allowing the output to accumulate phase faster than the reference. At t=t1, when the phase error has decreased to zero, Vcont returns to its initial value. Now, the two signals have equal frequencies and zero phase difference. Note also that the same goal can be accomplished by lowering the VCO frequency during this interval.
An ideal phase detector (PD) produces an output signal whose dc value is linearly proportional to the difference between the phases of two periodic inputs:
{overscore (Vout)}=KPDxcex94xcfx86
where KPD is the xe2x80x9cgainxe2x80x9d of the phase detector (specified in V/rad), and xcex94xcfx86 is the input phase difference. In practice, the characteristic may not be linear or even monotonic for large xcex94xcfx86. Furthermore, KPD may depend on the amplitude or duty cycle of the inputs.
A phase-locked loop is a feedback system that operates on the excess phase of nominally periodic signals. This is in contrast to familiar feedback circuits where voltage and current amplitudes, and their rate of change are of interest. A simple PLL, consists of a phase detector, a low-pass filter (LPF), and a VCO. The PD serves as an xe2x80x9cerror amplifierxe2x80x9d in the feedback loop, thereby minimizing the phase difference, xcex94xcfx86, between x(t) and y(t). The loop is considered xe2x80x9clockedxe2x80x9d if xcex94xcfx86 is constant with time, a result of which is that the input and output frequencies are equal.
In the locked condition, all the signals in the loop have reached a steady state and the PLL operates as follows. The phase detector produces an output whose dc value is proportional to xcex94xcfx86. The low-pass filter suppresses high-frequency components in the PD output, allowing the value to control the VCO frequency. The VCO then oscillates at a frequency equal to the input frequency and with a phase difference equal to xcex94xcfx86. Thus, the LPF generates the proper control voltage for the VCO.
It is important to note that in the above example the loop locks only after two conditions are satisfied: 1) xcfx89out has become equal to xcfx89in; and, 2) the difference between xcfx86in, and xcfx86out has settled to its proper value. If the two frequencies become equal at a point in time but xcex94xcfx86 does not establish the required control voltage for the VCO, the loop must continue the transient, temporarily making the frequencies unequal again. In other words, both xe2x80x9cfrequency acquisitionxe2x80x9d and xe2x80x9cphase acquisitionxe2x80x9d, or xe2x80x9ctrackingxe2x80x9d, must be completed. This is, of course, to be expected because for lock to occur again, all the initial conditions of the system, including the VCO output phase, must be updated.
Acquisition range is a critical parameter because 1) it trades directly with the loop bandwidth, and therefore, VCO gain. For example, if an application requires a small loop bandwidth, the acquisition range will be proportionally small; 2) it determines the maximum frequency variation in the input or the VCO that can be accommodated. In monolithic implementations, the VCO free-running frequency can vary substantially with temperature and process, thereby requiring a wide acquisition range even if the input frequency is tightly controlled.
FIG. 1 is a schematic block diagram of a PLL with aided frequency acquisition (prior art). Here, the system utilizes a frequency detector (FD) and a second low-pass filter, LPF2, whose output is added to that of LPF1. The FD produces an output having a dc value proportional to, and with the same polarity as xcfx89inxe2x88x92xcfx89out. If the difference between xcfx89in and xcfx89out is large, the PD output has a negligible dc component and the VCO is driven by the dc output of the FD with negative feedback, thereby moving xcfx89out toward xcfx89in. As |xcfx89inxe2x88x92xcfx89out| drops, the dc output of the FD decreases, whereas that of the PD increases. Thus, the frequency detection loop gradually relinquishes the acquisition to the phase-locked loop, becoming inactive when xcfx89inxe2x88x92xcfx89out=0.
It is important to note that in a frequency detection loop, the loop gain is relatively constant, independent of |xcfx89inxe2x88x92xcfx89out|, whereas in a simple phase-locked loop, it drops if |xcfx89inxe2x88x92xcfx89out| exceeds xcfx89LPF. For this reason, aided acquisition using FDs can substantially increase the capture range.
For a VCO in a PLL, the following parameters are important. 1) Tuning range: i.e., the range between the minimum and maximum values of the VCO frequency. In this range, the variation of the output amplitude and jitter must be minimal. The tuning range must accommodate the PLL input frequency range as well as process- and temperature-induced variations in the VCO frequency range. The tuning range is typically at least xc2x120%wFR. 2) Jitter and phase noise: timing accuracy and spectral purity requirements in PLL applications impose an upper bound on the VCO jitter and phase noise. 3) Supply and substrate noise rejection: if integrated along with digital circuits, VCOs must be highly immune to supply and substrate noise. When used, a frequency divider can corrupt the VCO output by injecting noise into the common substrate. Such effects become more prominent if a PLL shares the same substrate and package with a large digital processor.
Low VCO gain is a desirable feature as it reduces the circuit noise effects at the VCO output. Therefore, a less jittery, more stable VCO output is possible even on very high gate count mixed signal chips (with lots of power supply noise). However, in today""s high performance, low power mixed signal designs, low gain and low power fight against each other. These chips operate at low power because their supply voltages are down to 1.8 Volts or even lower, not necessarily because they draw less current from the power supply. Even though the low power supply voltage does not limit the oscillation frequency of a VCO, it puts a limit on the control voltage range in which VCO frequency is swept linearly. If the maximum and minimum oscillation frequencies obtain from the VCO are labeled Fmax and Fmin, respectively, and the control voltage range in which the VCO can be swept linearly xcex94V, the VCO gain is given as below:   VCO_Gain  =                    F        max            -              F        min                    Δ      ⁢              xe2x80x83            ⁢      V      
Therefore, as xcex94V gets smaller with low supply voltage values, the VCO gain becomes larger. To make the matters even worse, the process and temperature variations in CMOS circuits mandate that Fmax and Fmin be farther apart from each other to ensure the coverage of the actual operating frequency of interest under any condition, and thus causing even higher VCO gain.
It would be advantageous if a PLL with aided frequency acquisition circuit could be designed with a low noise output signal.
It would be advantageous if a PLL with an aided frequency acquisition circuit could be designed to have a minimal VCO frequency range during acquisition, but a larger frequency range during tracking.
It would be advantageous if the above-mentioned PLL with aided frequency acquisition circuit could be designed so that the acquisition occurred through the successive analysis of distinct frequency bands, so that the VCO gain could be minimized.
It would be advantageous if a PLL circuit could be designed to automatically select the frequency band of interest and the type of detector used in the acquisition and tracking of a data signal.
Accordingly, a method for acquiring and tracking a signal with a selectable frequency range VCO is provided. The method comprises: accepting a data signal having a first frequency; accepting a reference signal having approximately the first frequency; selecting a VCO range from a plurality of frequency ranges; acquiring the reference signal in response to selecting the VCO frequency range; and, increasing the frequency sweep to track the data signal.
In acquisition, the VCO signal is compared to the reference signal to detect frequency differences. In tracking, the VCO signal is compared to the data signal to detect phase differences. In response to detection, the VCO is supplied with a control voltage.
Following acquisition, the method comprises: sensing that the reference signal has been acquired; widening the frequency sweep window; and, switching from frequency detecting the reference signal to phase detecting the data signal, in response to sensing that the reference signal has been acquired.
If tracking is lost, the method comprises: switching from phase detecting the data signal to frequency detector the reference signal; while maintaining the larger frequency sweep window. Once reacquired, the method comprises: switching from frequency detecting the reference signal to phase detecting the data signal.
An auto-ranging phase-locked loop system for acquiring and tracking a data signal is also provided including a voltage controlled oscillator accepting frequency range commands, sweep window commands, and a control voltage. The VCO supplies a VCO signal having a frequency responsive to the control voltage and a frequency range responsive to the frequency range and sweep window commands. The PLL circuit also includes a frequency detector, phase detector, lock-detect circuit, and range circuit, as explained in more detail below.